Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology
October 17 2019 - 10:55AM
Business Wire
Samsung and Cadence collaborate to deliver an
integrated flow for designing analog and mixed-signal applications
at the 5nm node
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that
its custom and analog/mixed-signal (AMS) IC design flow has
achieved certification for Samsung Foundry’s 5nm Low-Power Early
(5LPE) process technology. This certification ensures mutual
customers of Cadence and Samsung Foundry have immediate access to a
highly automated circuit design, layout, signoff and verification
flow needed to design efficiently at 5LPE.
The automated Cadence® custom and AMS full flow supports the
company’s Intelligent System Design™ strategy, enabling SoC design
excellence. For more information on the Cadence custom and AMS flow
that supports the Samsung 5LPE process technology, visit
www.cadence.com/go/Samsung5LPE.
The certified Cadence custom and AMS flow enables customers to
develop their solutions using the 5LPE process for automotive,
mobile, data center, artificial intelligence (AI) and other
emerging applications. The tools in the flow incorporate key
features that are well suited for digitally assisted analog designs
such as high performance, best-in-class analysis and verification
capabilities developed in the Cadence Spectre® Accelerated Parallel
Simulator (APS). Additionally, the Cadence Virtuoso® Layout flow
provides a high level of automation and integration, enabling
faster design closure with reduced numbers of iterations critical
for completing complex designs at the 5LPE process.
The complete custom and AMS flow that is certified by Samsung
Foundry includes the Virtuoso Analog Design Environment (ADE),
Virtuoso Schematic Editor, Virtuoso Layout Suite, Virtuoso
Space-Based Router, Virtuoso Layout Suite EAD, Virtuoso Integrated
Physical Verification System, Spectre APS, Voltus™-Fi Custom Power
Integrity Solution, Quantus™ Extraction Solution, Litho Physical
Analyzer (LPA), LDE Electrical Analyzer (LEA) and Physical
Verification System (PVS). Key technical capabilities include:
- Circuit Design and Verification: Allows users to perform
static and dynamic circuit checks, DC/TRAN/AC/STB corner
simulation, transient noise simulation, Monte Carlo simulation and
high-yield estimation, electromigration and IR (EM-IR) analysis,
PSS-Pnoise and reliability analysis
- Custom Analog and Digital Layout: Offers users a
schematic-driven layout, automated constraint-driven pin-placement
and optimization, row-based device placement, layout-dependent
effects (LDE) analysis and hotspot detection, automated routing
with width spacing patterns (WSP) and pin-to-trunk features,
electrically aware design (EAD) for reduced iterations in achieving
electrically correct designs, in-design DRC verification using
signoff deck and automated digital block implementation
- Physical Verification and Signoff: Enables parasitic
extraction, custom constraint validation, post-layout simulation
with Detailed Standard Parasitic Format (DSPF), full-chip DRC and
layout versus schematic (LVS) signoff and design for manufacturing
(DFM) pattern-matching checks for detecting and correcting litho
hotspots and improving yields
In addition to the custom and AMS flow certification, a process
design kit (PDK) techfile is now Mixed-Signal Open Access-ready,
allowing customers to use the highly integrated Virtuoso-Innovus™
Implementation System flow. This enables users to create a layout,
and to perform static timing analysis and signoff for mixed-signal
designs more effectively and in a shorter amount of time.
“We’ve validated that the entire Cadence AMS flow meets our
requirements for designing at 5LPE technology,” said Jongshin Shin,
vice president of Foundry IP Development Team at Samsung
Electronics. “This high-performance flow represents a major
milestone in our ongoing collaboration. With the Cadence flow now
readily available, customers have access to advanced capabilities
needed to design applications more efficiently, while meeting
rigorous market requirements.”
“In collaboration with Samsung, we’ve achieved certification for
our integrated flow for AMS design at 5LPE to drive the advancement
of next-generation designs,” said Wilbur Luo, vice president,
product management in the Custom IC and PCB Group at Cadence.
“Based on the industry-leading Virtuoso and Spectre platforms, the
flow enables highly efficient design of AMS IP at this advanced
node for use in complex SoCs for mobile, data center and AI
applications.”
About Cadence
Cadence enables electronic systems and semiconductor companies
to create the innovative end products that are transforming the way
people live, work and play. Cadence software, hardware and
semiconductor IP are used by customers to deliver products to
market faster. The company’s Intelligent System Design strategy
helps customers develop differentiated products—from chips to
boards to intelligent systems—in mobile, consumer, cloud, data
center, automotive, aerospace, IoT, industrial and other market
segments. Cadence is listed as one of Fortune Magazine's 100 Best
Companies to Work For. Learn more at cadence.com.
© 2019 Cadence Design Systems, Inc. All rights reserved
worldwide. Cadence, the Cadence logo and the other Cadence marks
found at www.cadence.com/go/trademarks are trademarks or registered
trademarks of Cadence Design Systems, Inc. All other trademarks are
the property of their respective owners.
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