Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
April 18 2024 - 11:05AM
Efabless Corporation, the creator platform for chips, is pleased to
announce the release of OpenLane version 2, a major step forward in
the evolution of open-source electronic design automation tools.
OpenLane 2 is not merely an update; it is a re-envisioned
infrastructure that opens new possibilities for development
engineers and EDA tool developers to create custom flows, including
highly specialized steps that were previously unattainable in the
industry.
A Brief Overview of OpenLane
OpenLane is a Python-based infrastructure designed for
implementing Application-Specific Integrated Circuits (ASICs). The
OpenLane platform has been at the forefront of open-source silicon
implementation since 2020. Integrating a range of development tools
including Yosys, OpenROAD, Magic, and KLayout, it abstracts the
complex processes of silicon design into tangible and manageable
steps. This approach has made it the development backbone for
numerous projects, including most projects on the Open MPW and
chipIgnite shuttles.
OpenLane is more than a tool; it is a community-centric platform
that fosters collaboration and innovation in open-source hardware
design. Through OpenLane 2, Efabless is committed to pushing the
boundaries of open-source hardware into new territories.
OpenLane 2 transcends the mildly flexible flow of its
predecessor by providing a robust Python-based infrastructure upon
which users can construct fully customizable flows incorporating
both existing and novel steps using proprietary or open-source
tools.
Key Highlights of OpenLane 2:
- Stability and Flexibility: OpenLane 2
introduces a stable infrastructure that supports the creation of
multiple, customizable flows. Whether it is integrating custom
steps or leveraging advanced options for flow control, OpenLane 2
accommodates a wide range of user needs.
- Enhanced User Experience: Users benefit from
complete configuration validation, more graceful failure handling,
and the flexibility to resume flows from specific stages –
enhancing productivity and reducing time to implementation.
- Customizability at Its Core: With OpenLane 2,
users can write their own steps in Python, create complex flows
with decision-making capabilities, and even experiment within
Python Notebooks. This level of customization was previously not
possible.
Key Benefits
The OpenLane 2 tool flow also includes a number of additional
enhancements and benefits, including:
- Error-proof configuration and enhanced error handling
- Command-line flow control for nuanced workflow management
- Customizable and complex flows enabling optimal design
strategies
- Access to a standardized and formalized form of design
metrics
Mohamed Shalan, Head of the EDA/IC Design Team at Efabless,
remarked, "OpenLane 2 is a testament to our commitment to
innovation and collaboration in the open-source silicon space. By
offering a silicon development infrastructure that supports highly
customizable flows, we're not just meeting the current needs of the
industry – we're anticipating its future directions."
Availability
OpenLane 2 is now available. Download instructions can be found
at https://efabless.com/openlane
About Efabless
Efabless offers a platform applying open source and community
models to enable a global community of chip experts and non-experts
to collaboratively design, share, prototype and commercialize
special purpose chips. Over the past three years, 1300 designs and
six hundred tapeouts have been executed on Efabless. The company’s
customers include startups, Fortune 500 companies, universities,
and research institutions around the world. For more information,
please visit www.efabless.com.
Press Contact:
Andrea Vedanayagam
andrea@efabless.com
408.656.4494