SAN JOSE, Calif., March 10, 2016 /PRNewswire/ -- Xilinx, Inc.
(NASDAQ:XLNX) today announced it has developed a 16nm FinFET+-based
programmable device running 56G transceiver technology using the
4-level Pulse Amplitude Modulation (PAM4) transmission scheme.
Recognized by the industry as the most scalable signaling protocol
for next-generation line rates, PAM4 solutions will help drive the
next wave of Ethernet deployment for optical and copper
interconnects by doubling bandwidth on the existing infrastructure.
Xilinx is introducing and demonstrating 56G technology innovation
now, ahead of general PAM4 availability, to help educate and
prepare providers and ecosystem members to make this
transition.
Logo - http://photos.prnewswire.com/prnh/20020822/XLNXLOGO
"Our customers are already anticipating how to accelerate their
next generation applications. We recognize the need to raise
awareness of 56G PAM4 technology solutions now, to help prepare
them to transition their own designs," said Ken Chang, vice president of the SerDes
technology group at Xilinx. "I am delighted to be able to
showcase our technology."
As trends such as Cloud Computing, Industrial IoT, and
Software-Defined Networks continue to accelerate and drive the need
for unlimited bandwidth, technology innovations must scale to 50G,
100G, 400G ports, as well as terabit interfaces to maximize port
density without increasing cost and power per bit. Next generation,
standardized line rates are critical to meeting these ongoing
bandwidth requirements. Xilinx is leading in 56G PAM4
standardization efforts within both the Optical Internetworking
Forum (OIF) and the Institute of Electrical and Electronics
Engineers (IEEE). The company's 56G PAM4 transceiver technology has
been developed to break through the physical limitations of
traditional data transmission at such line rates, including
insertion loss and crosstalk. It supports copper and optical
interconnects for chip-to-chip, module, direct attach cable, or
backplane applications. It will enable next generation system
designs for beyond terabit line cards, 400G to terabit chassis
backplane.
Xilinx teamed with TSMC to ready its PAM4 device for 16nm
FinFET+ said TSMC North America vice president, Sajiv Dalal. "This transceiver
breakthrough is another milestone in our long and rewarding
collaboration with Xilinx. We share a commitment to
high-performance computing, and look forward to this demonstration
of Xilinx technology leadership later this month."
Xilinx will be showcasing the 56G PAM4 transceiver technology
demonstration at the upcoming OFC show (booth 3457), March 22 – 24, 2016 in Anaheim, California. For additional
information on the Xilinx 56G transceiver technology visit
http://www.xilinx.com/products/technology/high-speed-serial/56g.html.
About Xilinx
Xilinx is the leading provider
of All Programmable FPGAs, SoCs, MPSoCs, and 3D
ICs. Xilinx uniquely enables applications that are both software
defined and hardware optimized – powering industry advancements in
Cloud Computing, SDN/NFV, Video/Vision, Industrial IoT, and 5G
Wireless. For more information, visit www.xilinx.com
#1614
#AAB851
© Copyright 2016 Xilinx, Inc. Xilinx, the Xilinx logo, Artix,
ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated
brands included herein are trademarks of Xilinx in the United
States and other countries. All other trademarks are the property
of their respective owners.
Xilinx
Silvia E.
Gianelli
(408) 626-4328
silvia.gianelli@xilinx.com
To view the original version on PR Newswire,
visit:http://www.prnewswire.com/news-releases/xilinx-demonstrates-56g-pam4-transceiver-technology-300233783.html
SOURCE Xilinx, Inc.