Chartered Semiconductor Manufacturing (Nasdaq:CHRT) and
(SGX:CHARTEREDSC), one of the world�s top dedicated foundries,
today announced the general availability of an enhanced version of
its 65-nanometer (nm) low-power (LP) process, called 65nm LPe. The
65nm LPe process utilizes innovative leakage-reduction techniques
to significantly improve system-on-chip (SoC) standby power
consumption by up to 50 percent. The result is a lower-power
process especially suited for battery-operated and cost-sensitive
mobile applications that require active standby conditions, such as
mobile handsets, multimedia players or personal internet devices.
The process is also supported by a robust range of IP specifically
optimized for the lower leakage capabilities.
Chartered is also offering an optimized RF platform solution
based on the 65nm LPe process that combines RF physical design
kits, broad IP support and a collaborative development system with
its partners from the Wireless SoC Platform Alliance (WISPA)
consortium. (See additional press release from July 13, 2009:
�Chartered Offers 65nm RF Platform To Enable Single-Chip Wireless
Applications�).
The 65nm LPe process significantly improves the
performance-to-leakage ratio (Ion/Ioff) within the process�
pMOSFET. Given the same Ion (uA/um), the Ioff current is reduced by
a magnitude of 20X. This directly impacts the battery life of
mobile applications as this leakage improvement is observable in
both active and standby situations. In cases where a product
operates in long standby situations such as a mobile phone,
improvement in the standby power consumption can be as great as
15-25 percent, depending on the application.
A full suite of IP is available for the new process from leading
suppliers, including Analog Bits, Aragio Solutions, ARM, Cosmic
Circuits, Denali, Synopsys, True Circuits and Virage Logic. The
support includes analog front end (AFE), audio codecs, standard
interfaces and a range of level physical IP libraries and memory
compilers that have been specifically tuned to take advantage of
the enhanced leakage capabilities of the process.
�ARM is pleased to expand our long standing relationship with
Chartered by offering a full complement of physical IP optimized
for Chartered 65LPe process,� said Simon Segars, executive vice
president and general manager PIPD division, ARM. �This rich
platform of IP includes enhanced memories and logic targeted at
improving the performance of ARM processors. All products are
supported by the most advanced power management EDA views. We
believe this combination of 65LPe process and ARM physical IP is
well suited to a range of mainstream applications where leakage
optimization is paramount. Through the sponsorship of Chartered,
the libraries are free and available today at
http://designstart.arm.com.�
�We have worked closely with Chartered to optimize our SiWare�
Memory and SiWare� Logic solutions to their 65nm LPe process to
meet our mutual customers� SoC requirements,� said Brani Buric,
vice president of marketing and sales at Virage Logic. �With a
comprehensive dashboard of options, the SiWare product line
provides the flexibility needed to efficiently manage design
tradeoffs to meet low power as well as performance design
requirements.�
Chartered�s enhanced 65nm LPe process features a core 25
angstrom transistor oxide with three voltage options (Standard Vt,
Low Vt, High Vt). The High Vt option offers the lowest leakage at
0.01nA/um and 0.007nA/um for the NMOS and PMOS transistors,
respectively. Two thick gate oxides are available: a 32A device for
1.8V; and a flexible, IP-enabled 2.5V 52A device that is also
useable for 1.8V and 3.3V applications by varying the channel
length. The back end of line (BEOL) metal implementation supports
up to nine layers of copper to optimize die size and routing
efficiency. Manufactured on rotated substrates, the 65LPe process
benefits from an increase in the pMOSFET hole mobility and
saturation velocity without detrimentally affecting the
nMOSFET.
�Today�s high-volume mobile applications require highly
optimized silicon solutions that operate in an extremely
power-efficient manner, but don�t compromise performance or
functionality,� said Brian Klene, vice president, product marketing
at Chartered. �Our 65nm LPe process has been developed specifically
with extended battery life in mind, with optimizations made to the
process itself and our ecosystem of design support to improve
efficiency significantly. The 65nm LPe process is a full-featured
and flexible platform on which a wide variety of wireless, mobile
and multimedia products can be based.�
Industry Support for Chartered 65nm LPe Process
�The Chartered 65nm LPe process is well-suited for the demands
of power-sensitive mobile applications. With Analog Bits low-power,
clocking macros, programmable interconnects and specialized
memories, our customers can realize significant differentiation
with high yield and reliability. We have a long heritage and
well-proven track record of working closely with Chartered on each
successive process generation, and we can optimize our product
lines to work very efficiently with their underlying process. This
helps streamline the design flow for designers and allows our
technology to leverage the full potential of the advances Chartered
has made in its manufacturing technology.�
� Mahesh Tirupattur Executive VP Analog Bits, Inc. �
�Recognized worldwide as a premier IP provider, Aragio Solutions
has expanded the Chartered 65nm IO offerings to the LPe process
node. Using the knowledge and success of prior 65nm low-power and
generic process nodes, Aragio has been able to provide a full
complement of silicon-proven LPe IO libraries with excellent
electrical and ESD performance, enabling high-performance operation
for many industry standard interfaces - including USB 2.0,
Ethernet, LVDS, Mobile DDR and DDR - as well as RF and Analog ESD
protection circuitry. The diverse number of metal options made
available for clients points to the team effort required between
Chartered and Aragio to make this program successful.�
� Glen Haas, Chief Technologist Aragio Solutions �
�Cosmic Circuits, a leading provider of differentiated analog
and mixed-signal IP cores, has enjoyed a history of tight
partnership with Chartered, especially in the nanometer technology
nodes. We are happy that our joint efforts on the 65nm LPe node
have also been successful. It enables our common customers to
leverage a portfolio of silicon-proven mixed-signal cores,
including data-converters and power-management for low-power
portable applications. This was essentially possible through the
early access to Chartered�s process technology, and through the
R&D investments that Cosmic Circuits continually makes.
Following this launch, we look forward to serve customers actively
and experience all-around success.�
� Ganapathy Subramaniam CEO Cosmic Circuits �
�Denali and Chartered have taped out Denali�s LPDDR1/DDR2 memory
controller and digital PHY on the 65nm LPe process. Our customers
will be attracted to the enhanced speed of the Chartered 65nm LPe
process, where we�ve achieved timing at 800MT/s and transfer rates
up to 3.2GBytes/sec over a 32-bit DDR2 memory interface, while
giving the flexibility to support low-power LPDDR1 memories on the
same interface.�
� Marc Greenberg Director, Technical Marketing Denali Software �
�The 65nm process node is a mainstream design node for SoC
developers in the consumer multimedia markets in terms of its
low-power performance and production yield capabilities. We offer a
broad portfolio of analog IP including audio codecs and interface
IP, such as USB, HDMI, PCI Express and SATA for Chartered�s 65nm
LPe node to enable SoC designs to get to market faster with lower
risk.�
� John Koeter Vice President of Marketing for the Solutions Group
Synopsys, Inc. �
About Chartered
Chartered Semiconductor Manufacturing Ltd. (Nasdaq:CHRT)
(SGX:CHARTEREDSC), one of the world�s top dedicated semiconductor
foundries, offers leading-edge technologies down to 40/45 nanometer
(nm), enabling today�s system-on-chip designs. The company further
serves its customers� needs through a collaborative, joint
development approach on a technology roadmap that extends to 22nm.
Chartered�s strategy is based on open and comprehensive design
enablement solutions, manufacturing enhancement strategies, and a
commitment to flexible sourcing. In Singapore, the company owns or
has an interest in six fabrication facilities, including a 300mm
fabrication facility and five 200mm facilities. Information about
Chartered can be found at www.charteredsemi.com.
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