DVCon U.S. 2025 Announces Call for Extended Abstracts, Workshop & Tutorial Proposals
May 07 2024 - 12:23PM
The 2025 Design and Verification Conference and Exhibition United
States (DVCon U.S.), sponsored by Accellera Systems Initiative,
announces its call for extended abstract, workshop, and tutorial
proposals. The 37th annual DVCon U.S. will be held February 24-27,
2025, at the Doubletree Hotel in San Jose, California.
“Attending the Design and Verification Conference and Expo
offers an opportunity to learn about the latest advancements in
design and verification technologies, as well as gain insight into
emerging standards and strategies for tackling current challenges,”
stated Tom Fitzpatrick, DVCon U.S. 2025 General Chair. “The
Technical Program Committee welcomes your proposals focused on
practical experiences and innovative applications. Our commitment
is to provide attendees with an exceptional technical program,
fostering invaluable face-to-face connections among colleagues, a
longstanding hallmark of DVCon.”
Extended Abstract InformationThe call for
extended abstracts solicits papers and corresponding presentations
that are highly technical and reflect real-life experiences and
emerging trends in a variety of domains. Submissions are
encouraged, but not restricted to, the following topic areas:
Verification and Validation; Safety-Critical Design and
Verification; Machine Learning and Big Data; Design and
Verification Reuse and Automation; Mixed-Signal Design and
Verification; and Low-Power Design and Verification.
Submissions may incorporate the use of EDA tools; FPGA-based
designs; the use of specialized design and verification languages;
assertions in SVA or PSL; the use of general purpose and scripting
languages; applications of the Accellera Portable Stimulus
Standard; applications of design patterns or other innovative
language techniques; the use of AMS languages; and IoT
applications. Extended abstracts should be a minimum of 600 and no
more than 1200 words.
More information and guidelines can be found here.
As in the past, attendees will vote for the Stuart Sutherland
Best Paper and Best Poster awards to be presented toward the end of
the conference.
Sponsored Short Workshop and Tutorial
InformationShort workshops are sponsored 90-minute
sessions available to all attendees registered for the full
conference program. The workshops will be held on both Monday and
Thursday during the conference. Presenters of short workshops can
choose between a hands-on or lecture format.
The three-hour DVCon U.S. technical tutorials are available to
all attendees and are included in full conference registration. The
Committee is seeking sponsored tutorial topics that are current,
have a high-level of interest and offer strong continuing
educational content.
Suggested topics for both workshops and tutorials include:
SystemVerilog for verification and/or design; SystemC/C/C++ design
and/or verification of systems; SoC and software-driven
verification; Assertion-based verification, SystemVerilog
assertions, PSL, etc.; Coverage-driven verification; High-level
synthesis; Low-power design and verification techniques;
Secure/encrypted IP-based SoC design methods; Debug for design and
verification; Mixed-signal modeling and verification; Transaction
level modeling (TLM), ESL design, and IP integration (IP-XACT);
Functional Safety; Security; Embedded software verification;
Hardware/software co-development; Verification productivity
methods; Formal methodology and static analysis; Emulation; Post SI
debug; FPGA prototyping; Moving from proprietary solutions to
standards-based design and verification; Portable Stimulus;
Application-specific design verification challenges and techniques;
Machine learning applications for verification and design; and Open
source hardware/software/architecture.
Proposals should be an abstract of the workshop or tutorial, two
to five paragraphs and no more than 1,000 words. For more
information, including pricing, visit here.
Submission DeadlineThe submission site for all
proposals opens July 15. The deadline to submit extended abstracts,
tutorial and workshop proposals is September 9, 2024.
For inspiration and to view proceedings from past conferences,
visit the archives site.
About DVConDVCon is the premier conference for
discussion of the functional design and verification of electronic
systems. DVCon is sponsored by Accellera Systems Initiative, an
independent, not-for-profit organization dedicated to creating
design and verification standards required by systems,
semiconductor, intellectual property (IP) and electronic design
automation (EDA) companies. For more information about Accellera,
please visit www.accellera.org. For more information about DVCon
U.S., please visit here. Follow DVCon on Facebook, LinkedIn or
@dvcon_us on X or to comment, please use #dvcon_us.
For more information, please contact: |
Laura LeBlancConference Catalysts, LLC352-872-5544 Ext.
115lleblanc@conferencecatalysts.com |
|
Barbara BenjaminHighPointe
Communications503-209-2323barbara@hipcom.com |