Cadence Announces Tempus Power Integrity Solution for Signoff Timing-Aware IR Drop Analysis
November 06 2019 - 10:45AM
Business Wire
Highlights:
- Industry’s first integrated power integrity solution combines
STA with power analysis for more reliable, comprehensive signoff at
7nm and below
- Reduces IR drop margins to improve power and area without
sacrificing signoff quality in advanced-node, low-voltage
designs
- Utilizes proprietary vectorless-based algorithm to catch
worst-case power switching events, improving the reliability of IR
drop analysis without increased runtime
- Enables users to identify and automatically fix real silicon
failures before committing to tapeout
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the
Tempus™ Power Integrity Solution, the industry’s first
comprehensive static timing/signal integrity analysis and power
integrity analysis tool, which enables engineers to create reliable
designs at 7nm and below. The Tempus Power Integrity Solution is
the result of an integration between the widely used Cadence Tempus
Timing Signoff Solution and the Voltus™ IC Power Integrity
Solution. Using the new tool, customers can significantly lower IR
drop design margins without sacrificing signoff quality, thus
improving power and area. Early use cases demonstrated that the
Tempus Power Integrity Solution correctly identified IR drop
errors, avoiding silicon failure prior to tapeout and improving the
maximum frequency in silicon by up to 10%.
For more information on the Cadence Tempus Power Integrity
Solution, visit www.cadence.com/go/tempuspipr.
The new Tempus Power Integrity Solution combines the proven
Cadence Tempus Timing Signoff Solution and Voltus IC Power
Integrity Solution signoff engines, which let the designer assess
the overall timing impact on IR drop, reducing the engineering
workload and speeding design closure. The tool’s other key benefits
include:
- Smaller IR drop margins to improve power and area:
Intelligent activity generation and direct calculation of the
timing impact of IR drop reduces the need for larger safety
margins, optimizing power and area.
- Comprehensive signoff coverage: Vectorless activity
generation automatically develops activity vectors for full
coverage while also exploring potential failure scenarios on
voltage- sensitive paths, improving signoff IR drop analysis
reliability.
- Proprietary vectorless-based algorithm to identify
voltage-sensitive paths: Sensitivity analysis combined with
proprietary algorithms developed through machine learning (ML)
techniques efficiently identify critical paths most likely impacted
by IR drop. Tempus Power Integrity’s methods ensure a high degree
of IR drop analysis coverage without requiring extensive,
time-consuming vectors.
- Find and fix potential IR drop failures: Visibility into
voltage-sensitive high-risk failure scenarios allows designers to
catch potential problems early in the design cycle and fix them
automatically.
“IR drop analysis is a key signoff technology that is
increasingly critical, especially for today’s high-speed chips
operating with highly resistive lower metal layers,” said Marlin
Frederick, Jr., Fellow, Physical Design Group at Arm. “Our
evaluation of the Tempus Power Integrity Solution highlights that
Cadence’s integrated approach provides better coverage than
traditional vector-based flows for reasonable amounts of
compute.”
“Our relentless focus on creating deep integrations with our
complete RTL-to-GDS solution has made it possible to deliver new
capabilities that help customers achieve design excellence and in a
way that’s unprecedented in the industry,” Dr. Chin-Chi Teng,
senior vice president and general manager of the Digital &
Signoff Group at Cadence. “The Tempus Power Integrity Solution
resolves the issue of timing being dependent on IR drop, and
vice-versa. Additionally, our combined signoff engines provide
customers with a solution that’s faster and easier to use.”
The Tempus Power Integrity Solution is part of the broader
Cadence digital implementation and signoff full flow, which
provides customers with a fast path to design closure and better
predictability. The new tool supports the company’s Intelligent
System Design™ strategy, enabling advanced-node system-on-chip
(SoC) design excellence.
About Cadence
Cadence enables electronic systems and semiconductor companies
to create the innovative end products that are transforming the way
people live, work and play. Cadence software, hardware and
semiconductor IP are used by customers to deliver products to
market faster. The company’s Intelligent System Design strategy
helps customers develop differentiated products—from chips to
boards to intelligent systems—in mobile, consumer, cloud, data
center, automotive, aerospace, IoT, industrial and other market
segments. Cadence is listed as one of Fortune Magazine's 100 Best
Companies to Work For. Learn more at cadence.com.
© 2019 Cadence Design Systems, Inc. All rights reserved
worldwide. Cadence, the Cadence logo and the other Cadence marks
found at www.cadence.com/go/trademarks are trademarks or registered
trademarks of Cadence Design Systems, Inc. Arm is a registered
trademark of Arm Limited (or its subsidiaries) in the US and/or
elsewhere. All other trademarks are the property of their
respective owners.
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