PITTSBURGH, May 6, 2014 /PRNewswire/ -- ANSYS, Inc.
(NASDAQ: ANSS) today introduced 2014 version of
RedHawk™, the industry-standard power noise and
reliability sign-off platform ready for FinFET-based designs. The
new release delivers greater performance, capacity and coverage, as
well as sign-off accuracy to address the challenges faced by the
increasing complexity of FinFET-based designs.
To meet the demands of lower power consumption and higher
operating performance in today's mobile, computing, consumer and
automotive electronics, integrated circuit (IC) designers are
adopting FinFET technology – a three-dimensional transistor
architecture in which the elevated channel is wrapped by a gate
electrode. While FinFET brings many benefits, these designs
experience smaller noise and reliability margins, which require
tighter control over analysis accuracy.
Capacity and Performance
To meet sign-off quality,
system-on-chip (SoC) dynamic voltage drop analysis requires a flat
modeling framework to accurately predict the current flow inside
tightly coupled elements across chip, package and the printed
circuit board (PCB). Due to the global nature of power delivery
network, a more traditional hierarchical approach cannot deliver
the accuracy needed for sign-off. RedHawk version 2014 offers
Distributed Machine Processing (DMP) capabilities that deliver on
average three times improvement in memory footprint, enabling the
simulation of more than 100 million instances or over 2 billion
nodes, while maintaining flat simulation accuracy. DMP's
proprietary architecture takes advantage of the increased
processing power and memory capacity available in a private machine
cluster to simulate each module within the context of the entire
chip, including package and PCB elements.
Along with DMP, this release employs software architecture
changes and flow optimizations to deliver two to three times
runtime improvements over its previous release, which was already
the fastest power integrity solution in the market. The combination
of DMP and architecture improvements bring capacity and performance
required for today's ultra large designs, especially those
fabricated using FinFET technologies, without compromising sign-off
accuracy.
Chip-Package Co-Analysis
With the increasing size of
SoC, along with variations in the switching current and parasitic
profile across the chip, the connection between SoC and package
needs to be as granular as possible to deliver quality sign-off.
RedHawk version 2014 introduces RedHawk-CPA, the industry's first
integrated chip-package co-simulation and co-analysis solution.
This new option maps the package to the die layout, through
pin-to-pin physical connectivity – seamlessly merging a fully
distributed package parasitic network with an on-die power delivery
network. By incorporating both chip and package layouts in the same
simulation environment, RedHawk-CPA provides immediate feedback on
the quality of the package design, as well as the impact of package
parasitic on the chip's performance.
Foundry-Certified Reliability
FinFET-based designs
introduce tighter electromigration (EM) limits and a new class of
EM rules, as well as greater thermal impact on EM reliability.
RedHawk version 2014 is foundry certified for IR-drop and EM
analysis for the latest process technology. It supports advanced EM
rules that consider current flow direction, metal topology and via
types for both power and signal nets. In addition, this release
enables thermal-aware EM analysis by providing chip thermal model
(CTM) that accurately captures the thermal distribution that is
critical for FinFET devices with greater self-heating issues.
"Over the past decade, RedHawk has been the industry standard
for power integrity and sign-off by the world's top 20
semiconductor companies," said Aveek
Sarkar, vice president of product engineering and support
from ANSYS. "As the industry adopts new FinFET technology, our
customers face increasing challenges in meeting their power,
performance and price targets. The release of RedHawk version 2014
demonstrates our commitment in continuing to deliver innovative
technologies to meet our customers' next-generation low-power,
high-performance design requirements."
The ANSYS portfolio of product offerings will be showcased at
the Design Automation Conference (DAC) June
2-6 in exhibit booth #1413.
About ANSYS, Inc.
ANSYS brings clarity and
insight to customers' most complex design challenges through fast,
accurate and reliable engineering simulation. Our technology
enables organizations ― no matter their industry ― to predict with
confidence that their products will thrive in the real world.
Customers trust our software to help ensure product integrity and
drive business success through innovation. Founded in 1970, ANSYS
employs more than 2,600 professionals, many of them expert in
engineering fields such as finite element analysis, computational
fluid dynamics, electronics and electromagnetics, and design
optimization. Headquartered south of Pittsburgh, U.S.A., ANSYS has more than 75 strategic sales
locations throughout the world with a network of channel partners
in 40+ countries. Visit www.ansys.com for more information.
ANSYS also has a strong presence on the major social channels.
To join the simulation conversation, please visit:
www.ansys.com/Social@ANSYS
ANSYS and any and all ANSYS, Inc. brand, product, service and
feature names, logos and slogans are registered trademarks or
trademarks of ANSYS, Inc. or its subsidiaries in the United States or other countries.
All other brand, product, service and feature names or
trademarks are the property of their respective owners.
ANSS-G
Contact
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Media
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Yukari Ohno
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408.457.2000
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yukari.ohno@ansys.com
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Tom
Smithyman
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724.514.3076
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tom.smithyman@ansys.com
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Investors
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Annette Arribas
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724.514.1782
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annette.arribas@ansys.com
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SOURCE ANSYS, Inc.