WILSONVILLE, Ore., Nov. 10, 2015 /PRNewswire/
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Highlights:
- New verification IP (VIP) for ARM® AMBA®
5 AHB specification speeds development of embedded and
Internet-of-Things (IoT) products
- Increases productivity in verifying hardware and software in
complex products
- Extends coverage of Mentor® VIP for a new generation of
ARM-based SoCs
Mentor Graphics Corporation (NASDAQ: MENT) today
announced availability of verification IP (VIP) for the ARM AMBA 5
AHB on-chip interconnection specification. Available in the
Mentor® Enterprise Verification Platform™ (EVP), this
new VIP simplifies and speeds up the verification process for
designers using Questa® simulation and
Veloce® emulation to verify chip designs using the new
specification.
As part of the Mentor® VIP library, the new VIP
provides essential information for verifying designs using the
interconnect specification—sequences, test plans, coverage and
assertions for the memory types, and security and messaging
features.
"The ARM AMBA 5 AHB specification defines on-chip connectivity
that is area-efficient, low-latency, and low-power for ARM-based
embedded and IoT solutions," said Andy
Nightingale, vice president of system IP marketing, systems
and software group, ARM. "Mentor Graphics is providing verification
IP to simplify development of interconnects for the next generation
of ARM-based SoCs to meet the growing demand of the IoT and
embedded markets."
The Mentor VIP library provides engineers with standard UVM
SystemVerilog (SV) components using a common architecture across
all protocols. This allows rapid deployment of multiple protocols
within a verification team. Test plans, compliance tests, test
sequences and protocol coverage are all included as SV and XML
source code, allowing simple re-use, extension and customization.
The Mentor VIP components also include a comprehensive set of
protocol checks, error injection and debug capabilities.
"The ARM AMBA 5 AHB expands our industry-leading support for
AMBA in the Mentor VIP library," said Mark
Olen, product manager, Design Verification Technology
Division. "Combined with our EZ-VIP productivity package, the
Mentor VIP library helps all ARM-based SoC designers and
verification engineers identify bugs quickly and reduce overall
time to market."
By providing AMBA 5 AHB VIP for use with Questa and Veloce
platforms, the EVP helps designers debug block-to-block
interactions in simulation, as well as fully verify system-level
software running on virtual hardware using high-performance
simulation acceleration. Questa simulation brings a complete
interactive debug environment, Veloce emulation delivers the
highest performance system-level verification throughput, and now
both provide complete functional support of the AMBA 5 AHB
specification.
Mentor verification IP is a key part of the EVP, which combines
Questa® advanced verification solutions, Veloce
emulation platform, and the Visualizer™ debug
environment into a globally accessible, high-performance,
datacenter resource. The Mentor EVP features global resource
management that supports project teams around the world, maximizing
both user productivity and total verification return on
investment.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic
hardware and software design solutions, providing products,
consulting services and award-winning support for the world's most
successful electronic, semiconductor and systems companies.
Established in 1981, the company reported revenues in the last
fiscal year in excess of $1.24
billion. Corporate headquarters are located at 8005 S.W.
Boeckman Road, Wilsonville, Oregon
97070-7777. World Wide Web site: http://www.mentor.com/.
Mentor Graphics and Questa are registered trademarks of Mentor
Graphics Corporation. All other company or product names are the
registered trademarks or trademarks of their respective owners.
For more information, please contact:
David Smith
Mentor Graphics
503.685.1135
david_smith@mentor.com
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SOURCE Mentor Graphics Corporation